![]() ![]() The serial-parallel converter as claimed in claim 1, wherein each of said plurality of data extraction units comprises:Ī flip-flop circuit operable in synchronizing with said clock signal andĪ selector connected to said flip-flop circuit for receiving an output value from said flip-flop circuit so that said selector selects one of said output value from said flip-flop circuit and said bit value of said serial data to render selected one inputted into said flip-flop circuit.ģ. ![]() A serial-parallel converter comprising:Ī plurality of data extraction units for sequentially extracting different bit values of serial data, which are sequentially inputted, for individually holding said different bit values for a time period corresponding to the same number of cycles of a clock signal as the number of said data extraction units until said plurality of data extraction units extract next bit values of said serial data Ī delay unit connected to said plurality of data extraction units for receiving data signals from said plurality of data extraction units and delaying said data signals to generate delay signals which synchronize with each other andĪ parallel register connected to said delay unit for receiving said delay signals from said delay unit for latching said delay signals to output said delay signals simultaneously as parallel data.Ģ.
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